Pontificia Universidad Católica de Chile Pontificia Universidad Católica de Chile
Patent A1 20190189803 (2019)

SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES

Revista : Patente
Tipo de publicación : Otros Ir a publicación

Abstract

Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure