Passive reference-sharing SAR ADC

Abstract

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely usedfor their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming toreduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, suchas splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors inmultiple steps. In this paper, a fully-dierential, low-power, passive reference voltage sharing SAR ADC architecturefor wireless sensor network (WSN) applications is presented, along with its theoretical analysis and test results. In thisarchitecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down bysuccessively connecting equally-sized capacitors in parallel, allowing the use small capacitor for its implementation.The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoMbetween 39.5 and 49.5 fJ per conversion step.